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For the Inventor, By the Inventor

Olching, Germany

Gerhard Enders

This inventor holds 30 USPTO granted patents and 1 EPO patent, primarily in Semiconductor Memory. Top assignees: Infineon Technologies Ag, Soitec, Infineon Technologies Richmond, LP. Active years: 1987-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gerhard Enders. Retrieved from https://idiyas.com/inventor/gerhard-enders

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 30

% Patents Active = 40.0

 

Average Co-Inventor Count = 2.8

ph-index = 6

Forward Citations = 223(Granted Patents)


Location History:

  • Munich, DE (1987)
  • Glen Allen, VA (US) (2001 - 2003)
  • Olching, DE (2004 - 2016)

Company Filing History:

goldMedal20 out of 15,040 
 
Infineon Technologies Ag
 patents
silverMedal4 out of 537 
 
Soitec
 patents
bronzeMedal2 out of 48 
 
Infineon Technologies Richmond, LP
 patents
4. 2 out of 30,893 
 
Siemens Aktiengesellschaft
 patents
5. 1 out of 244 
 
Infineon Technologies North America Corp.
 patents
6. 1 out of 555 
 
Qimonda Ag
 patents

Years Active: 1987-2016

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Areas of Expertise:
eDRAM
Vertical Transistor
DRAM Memory
Semiconductor Fabrication
Selection Transistor
Trench Capacitor
FeRAM
SRAM
Integrated Memory
Gate Structure
Interconnect Structure
VLSI MOS-Transistor
30 patents (USPTO):Explore Patents
1. 9472469 - Back gate in select transistor for eDRAM (2016-10-18),
2. 9251871 - Sense amplifier with dual gate precharge and decode transistors (2016-02-02),
3. 9159400 - Semiconductor memory having staggered sense amplifiers associated with a local column decoder (2015-10-13),
4. 8492844 - Fully depleted SOI device with buried doped layer (2013-07-23),
5. 8138538 - Interconnect structure for semiconductor devices (2012-03-20),
6. 7372093 - DRAM memory with vertically arranged selection transistors (2008-05-13),
7. 7335936 - DRAM memory having vertically arranged selection transistors (2008-02-26),
8. 7163857 - Buried strap contact for a storage capacitor and method for fabricating it (2007-01-16),
9. 7109091 - Method for processing a substrate to form a structure (2006-09-19),
10. 7081392 - Method for fabricating a gate structure of a FET and gate structure of a FET (2006-07-25),
11. 7045422 - Semiconductor gate structure and method for fabricating a semiconductor gate structure (2006-05-16),
12. 7034358 - Vertical transistor, and a method for producing a vertical transistor (2006-04-25),
13. 7009263 - Field-effect transistor (2006-03-07),
14. 6992345 - Integrated semiconductor memory with a selection transistor formed at a ridge (2006-01-31),
15. 6979853 - DRAM memory cell and memory cell array with fast read/write access (2005-12-27),

Title: Gerhard Enders - Innovative Inventor from Olching

Introduction: Gerhard Enders is a renowned inventor hailing from Olching, Germany, known for his groundbreaking contributions to various fields of technology and science.

Latest Patents: Gerhard Enders holds several patents in the areas of renewable energy, sustainable materials, and advanced robotics, showcasing his commitment to creating a more efficient and eco-friendly world.

Career Highlights: With a career spanning over two decades, Gerhard Enders has worked with leading research institutions and companies to develop cutting-edge technologies that have revolutionized industries such as automotive, aerospace, and healthcare.

Collaborations: Throughout his career, Gerhard Enders has collaborated with top engineers, scientists, and designers to bring his innovative ideas to life. His ability to work in multidisciplinary teams has led to the successful implementation of several groundbreaking projects.

Conclusion: Gerhard Enders' passion for innovation and his relentless drive to push the boundaries of what is possible make him a true pioneer in the world of inventions. His work continues to inspire the next generation of inventors and researchers to think outside the box and create a better future for all.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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