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Sandston, VA, United States of America

Infineon Technologies Richmond, LP

USPTO Granted Patents = 48

% Expired Patents = 52.1

Forward Citations = 450

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89 inventors (with patents filed for the assignee):

Joerg Vollrath (6 out of 32 patents)

Robert Petter (4 out of 5 patents)

Christopher Gould (4 out of 5 patents)

4. William Roberts (4 out of 5 patents)

5. Randall J Rooney (3 out of 51 patents)

6. Dieter Rathei (3 out of 7 patents)

7. Ulrich Zimmermann (3 out of 10 patents)

8. Mark Daniel Eubanks (2 out of 9 patents)

9. Michael Rennie (2 out of 18 patents)

10. Thomas Schulz (2 out of 50 patents)

11. Gerhard Enders (2 out of 30 patents)

12. Lothar Risch (2 out of 55 patents)

13. Heinrich Ollendorf (2 out of 3 patents)

14. Igor Jekauc (2 out of 2 patents)

15. Francis Goodwin (2 out of 2 patents)

Core Competencies:

Semiconductor Devices

Deep Trench Structures

Wafer Placement

Memory Device Analysis

Lithography Correction

Yield Prediction

DRAM Performance

Etch Process Monitoring

Bit-Fail Map

Electrical Testing

Capacitor Design

Process Controller

48 patents: Sort by Forward Citations

1. 7427774 - Targets for measurements in semiconductor devices (2008-09-23),

2. 7402487 - Process for fabricating a semiconductor device having deep trench structures (2008-07-22),

3. 7381576 - Method and apparatus for monitoring precision of water placement alignment (2008-06-03),

4. 7358493 - Method and apparatus for automated beam optimization in a scanning electron microscope (2008-04-15),

5. 7351642 - Deglaze route to compensate for film non-uniformities after STI oxide processing (2008-04-01),

6. 7300875 - Post metal chemical mechanical polishing dry cleaning (2007-11-27),

7. 7279258 - Method and arrangement for controlling focus parameters of an exposure tool (2007-10-09),

8. 7214552 - Eliminating systematic process yield loss via precision wafer placement alignment (2007-05-08),

9. 7184853 - Lithography method and system with correction of overlay offset errors caused by wafer processing (2007-02-27),

10. 7150796 - [object Object] (2006-12-19),

11. 7127304 - System and method to predict the state of a process controller in a semiconductor manufacturing facility (2006-10-24),

12. 7051253 - Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment (2006-05-23),

13. 7017429 - Continuous test flow method and apparatus (2006-03-28),

14. 7009193 - Utilization of an ion gauge in the process chamber of a semiconductor ion implanter (2006-03-07),

15. 7003432 - Method of and system for analyzing cells of a memory device (2006-02-21),

Company Overview

Infineon Technologies Richmond, LP, located in Sandston, Virginia, specializes in the development and manufacturing of advanced semiconductor devices. The company focuses on innovative technologies such as deep trench structures and wafer placement alignment, which are critical for enhancing device performance and reliability. Infineon's expertise extends to various processes, including scanning electron microscopy, chemical mechanical polishing, and lithography methods, contributing to the advancement of memory device analysis and electrostatic damage protection in semiconductor applications.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

48 Patents

#1 in Sandston, VA

#121 in Virginia

#7,288 in US

#14,561 in the World

Sandston, VA, United States of America

Infineon Technologies Richmond, LP

Forward Citations = 450

89 inventors:

Joerg Vollrath (6 out of 32 patents)

Robert Petter (4 out of 5 patents)

Christopher Gould (4 out of 5 patents)

4. William Roberts (4 out of 5 patents)

5. Randall J Rooney (3 out of 51 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Infineon Technologies Richmond, LP. Retrieved from https://idiyas.com/company/infineon-technologies-richmond

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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