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For the Inventor, By the Inventor

Hsinchu, Taiwan

Fang-Wei Lee

This inventor holds 33 USPTO granted patents and 23 published patent applications, primarily in Semiconductor Manufacturing. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., TSMC Nanjing Company, Limited. Active years: 2020-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fang-Wei Lee. Retrieved from https://idiyas.com/inventor/fang-wei-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 

% Patents Active = 100.0

Average Co-Inventor Count = 6.4

ph-index = 3

Forward Citations = 14(Granted Patents)


Company Filing History:

goldMedal33 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal2 out of 115 
 
TSMC Nanjing Company, Limited
 patents
where one patent can have more than one assignee

Years Active: 2020-2026

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Areas of Expertise:
Semiconductor Device
FinFET
Etching Techniques
Interconnect Structure
Inner Spacer
Self-Aligned Barrier
Nanowire
Fabrication Method
Multi-Gate Transistors
Germanium Etching
Baking Module
Spacer Structure
33 patents (USPTO):Explore Patents
1. 12745414 - Semiconductor device and manufacturing method thereof (2026-09-22),
2. 12520558 - High selectivity etching with germanium-containing gases (2026-01-06),
3. 12471344 - Dry etching of semiconductor structures with fluorine-containing gases (2025-11-11),
4. 12402394 - Semiconductor structure (2025-08-26),
5. 12389619 - Semiconductor device structure with inner spacer layer (2025-08-12),
6. 12376337 - Air inner spacers (2025-07-29),
7. 12336252 - Inner spacer formation in multi-gate transistors (2025-06-17),
8. 12334435 - Middle-of-line interconnect structure and manufacturing method (2025-06-17),
9. 12266538 - Method for manufacturing semiconductor device using etchant composition having high etching selectivity (2025-04-01),
10. 12224210 - Method for FinFet fabrication and structure thereof (2025-02-11),
11. 12218219 - Spacer structure for semiconductor device (2025-02-04),
12. 12198939 - Technique for semiconductor manufacturing (2025-01-14),
13. 12033863 - Semiconductor fabrication system embedded with effective baking module (2024-07-09),
14. 12021125 - High selectivity etching with germanium-containing gases (2024-06-25),
15. 12009294 - Middle-of-line interconnect structure and manufacturing method (2024-06-11),

Title: The Innovative Journey of Inventor Fang-Wei Lee

Introduction:

Fang-Wei Lee, a distinguished inventor hailing from Hsinchu, Taiwan, has made significant contributions to the field of technology and innovation through his groundbreaking inventions and patents.

Latest Patents:

Lee's latest patents include cutting-edge technologies in the semiconductor industry, particularly in the development of advanced microchips and nanotechnology applications. His innovative solutions have garnered international recognition for their impact on the industry.

Career Highlights:

With a career spanning over two decades, Fang-Wei Lee has held key positions in leading tech companies, where he spearheaded research and development projects that have revolutionized the way we perceive technology. His expertise in semiconductor physics and materials science has been instrumental in shaping the future of the industry.

Collaborations:

Throughout his career, Lee has collaborated with top research institutions and universities worldwide to further his research and bring his inventions to life. His ability to work across disciplines and cultures has led to the successful implementation of cutting-edge technologies in various sectors.

Conclusion:

Inventor Fang-Wei Lee's relentless pursuit of innovation and his passion for pushing the boundaries of technology have solidified his position as a visionary in the field. His contributions continue to inspire the next generation of inventors and pave the way for a more technologically advanced future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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