The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 01, 2023
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc Nanjing Company Limited, Nanjing, CN;

Inventors:

Han-Yu Lin, Nantou County, TW;

Fang-Wei Lee, Hsinchu City, TW;

Kai-Tak Lam, Hsinchu City, TW;

Raghunath Putikam, Hsinchu City, TW;

Tzer-Min Shen, Hsinchu City, TW;

Li-Te Lin, Hsinchu City, TW;

Pinyen Lin, Rochester, NY (US);

Cheng-Tzu Yang, Hsinchu County, TW;

Tzu-Li Lee, Yunlin County, TW;

Tze-Chung Lin, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0243 (2025.01); H10D 30/62 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 30/6219 (2025.01);
Abstract

A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an Fgas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.


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