Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Fang-Wei Lee

Pinyen Lin

Li-Te S Lin

Han-Yu Lin

Tze-Chung Lin

Chansyun David Yang

Fo-Ju Lin

Sung-Li Wang

Chia-Hung Chu

Yi-Ruei Jhan

Jung-Hao Chang

Chung-Liang Cheng

Ziwei Fang

Keng-Chu Lin

Huang-Lin Chao

Mrunal Abhijith Khaderbad

Cheng-Wei Chang

Hung-Chang Sun

Hsiang-Pi Chang

Chao-Hsien Huang

Yi-Ying Liu

Akira Mineji

Yao-Sheng Huang

Yi-Lun Chen

Yu-Wei Lu

Yu-Yun Peng

Shuen-Shin Liang

I-Ming Chang

Yi-Chen Lo

Kenichi Sano

Huan-Chieh Su

Tzer-Min Shen

Chih-Ching Wang

Gwan-Sin Chang

Chun-Yu Chen

Tzu-Li Lee

Meng-Huan Jao

I-ming Chang

Chih-Long Chiang

Cheng-Tzu Yang

Raghunath Putikam

Chia-Chien Kuang

Kai-Tak Lam

The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

Dry etching of semiconductor structures with fluorine-containing gases

A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.

Semiconductor structure

A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Semiconductor device structure with inner spacer layer

The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

Air inner spacers

A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

Inner spacer formation in multi-gate transistors

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Middle-of-line interconnect structure and manufacturing method

A method for manufacturing a semiconductor device includes:

Method for manufacturing semiconductor device using etchant composition having high etching selectivity

A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

Method for FinFet fabrication and structure thereof

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

Spacer structure for semiconductor device

A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.

Technique for semiconductor manufacturing

The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

Semiconductor fabrication system embedded with effective baking module

The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

High selectivity etching with germanium-containing gases

An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Self-aligned barrier for metal vias

A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

Semiconductor device structure with inner spacer layer and method for forming the same

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Hsinchu, Taiwan

Fang-Wei Lee