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For the Inventor, By the Inventor

Zhubei, Taiwan

Fang-Ting Kuo

This inventor holds 18 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Technology. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fang-Ting Kuo. Retrieved from https://idiyas.com/inventor/fang-ting-kuo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18 

% Patents Active = 100.0

Average Co-Inventor Count = 3.3

ph-index = 2

Forward Citations = 9(Granted Patents)


Location History:

  • Zhubei, TW (2017 - 2021)
  • Hsinchu County, TW (2018 - 2023)
  • Hsinchu, TW (2023 - 2024)

Company Filing History:

goldMedal18 out of 43,487 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2017-2026

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Areas of Expertise:
Semiconductor Device
Metal Insulator Capacitor
Gate Structure
CMP Loading Effect
Barrier Layer
Capping Structure
TSV
Metal Pad Structures
Low Noise Device
Grain Size Control
Device Formation
Semiconductor Structures
18 patents (USPTO):Explore Patents
1. 12772546 - Semiconductor device structure and methods of forming the same (2026-10-20),
2. 12363987 - Partial metal grain size control to improve CMP loading effect (2025-07-15),
3. 12218181 - Barrier layer for metal insulator metal capacitors (2025-02-04),
4. 12211890 - Barrier layer for metal insulator metal capacitors (2025-01-28),
5. 12166104 - Gate structure and methods thereof (2024-12-10),
6. 11978781 - Partial metal grain size control to improve CMP loading effect (2024-05-07),
7. 11830889 - Semiconductor device and method of forming the same (2023-11-28),
8. 11799014 - Gate structure and methods thereof (2023-10-24),
9. 11227935 - Gate structure and methods thereof (2022-01-18),
10. 11094723 - Semiconductor device and method of forming the same (2021-08-17),
11. 11011556 - Method of making a semiconductor device (2021-05-18),
12. 10535686 - Semiconductor device and method of forming the same (2020-01-14),
13. 10431664 - Gate structure and methods thereof (2019-10-01),
14. 10157990 - Semiconductor device with capping structure and method of forming the same (2018-12-18),
15. 10050103 - Method of forming semiconductor structures including metal insulator metal capacitor (2018-08-14),

Title: Fang-Ting Kuo: Innovator in Semiconductor Technology

Introduction

Fang-Ting Kuo is a prominent inventor based in Zhubei, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 18 patents. His work focuses on improving the efficiency and effectiveness of semiconductor structures.

Latest Patents

Among his latest patents is a groundbreaking invention titled "Partial metal grain size control to improve CMP loading effect." This patent describes a semiconductor structure that includes a substrate with distinct active regions, gate structures, and dopants in the gate electrodes. Another notable patent is for a "Barrier layer for metal insulator metal capacitors," which outlines a method for fabricating MiM capacitor structures with nitrogen-rich metal nitride layers. This method involves the careful deposition of electrode bilayers and dielectric layers to enhance capacitor performance.

Career Highlights

Fang-Ting Kuo is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leader in the semiconductor industry. His innovative work has positioned him as a key figure in advancing semiconductor technologies.

Collaborations

Fang-Ting has collaborated with notable colleagues, including Anhao Cheng and Victor Chiang Liang. Their combined expertise has contributed to the successful development of various semiconductor technologies.

Conclusion

Fang-Ting Kuo's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the industry. His work continues to pave the way for advancements in semiconductor structures and applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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