San Jose, CA, United States of America

Fadi Maamari

This inventor holds 13 USPTO granted patents, primarily in Circuit Design Testing. Top assignees: Synopsys, Inc., Logicvision, Inc., Atrenta, Inc.. Active years: 2002-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fadi Maamari. Retrieved from https://idiyas.com/inventor/fadi-maamari

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 92.3

Average Co-Inventor Count = 3.2

ph-index = 5

Forward Citations = 79(Granted Patents)


Location History:

  • San Jose, CA (US) (2002 - 2023)
  • Mountain View, CA (US) (2023)

Company Filing History:


Years Active: 2002-2026

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Areas of Expertise:
Circuit Elements
Threat Analysis
Machine Learning
Design For Test
Test Pattern Generation
Scan Chain
Failure Mode
Integrated Circuit
System On Chip
Clocking Methodology
High Performance Circuits
Bus Conflict Detection
13 patents (USPTO):Explore Patents

Title: The Innovative Mind of Fadi Maamari: Pioneering Success in Circuit Design

Introduction: Fadi Maamari, an accomplished inventor based in San Jose, California, has made significant contributions to the field of circuit design and testing. With a remarkable portfolio of 10 patents, Maamari's work focuses on advancing techniques in automated failure mode distribution and machine-learning-based design-for-test systems. His innovative approaches are shaping the future of integrated circuit design and testing protocols.

Latest Patents: Among Maamari's latest patents is a groundbreaking method titled "Automated Determination of Failure Mode Distribution." This method traces from an observation point in a circuit to produce a cone of influence that encompasses various components connected at multiple nodes. By determining an observability probability for each node, along with a weighted soft error probability for each logic element, the method establishes a comprehensive failure mode distribution for the entire circuit. Another notable patent is the "Machine-learning-based Design-for-Test (DFT) Recommendation System for Improving Automatic Test Pattern Generation (ATPG) Quality of Results (QOR)." This innovative approach utilizes machine learning to analyze training data collected from integrated circuit designs, leading to predictions of ranked test-case configurations that enhance test coverage.

Career Highlights: Fadi has held positions at notable companies, including LogicVision, Inc. and Synopsys, Inc. His roles in these organizations have enabled him to refine his expertise and drive forward innovative projects impacting the circuit design industry positively.

Collaborations: Throughout his career, Maamari has collaborated with prominent professionals such as Benoit Nadeau-Dostie and Dwayne M. Burek. These collaborations have fostered the exchange of ideas and techniques, further enriching Maamari's inventive processes and contributions to the field.

Conclusion: Fadi Maamari's innovative spirit and technical prowess have paved the way for advances in circuit design and testing methodologies. With numerous patents to his name, he continues to push the boundaries of what is possible in the realm of integrated circuits, influencing future developments and inspiring the next generation of inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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