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San Jose, CA, United States of America

Atrenta, Inc.

USPTO Granted Patents = 47

Trademarks = 2

Forward Citations = 279

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69 inventors (with patents filed for the assignee):

Mohammad Homayoun Movahed-Ezazi (11 out of 15 patents)

Solaiman Rahim (7 out of 19 patents)

Mohamed Shaker Sarwary (6 out of 12 patents)

4. Maher Mneimneh (5 out of 9 patents)

5. Anshuman Nayak (5 out of 6 patents)

6. Samantak Chakrabarti (5 out of 6 patents)

7. Brijesh Agrawal (5 out of 7 patents)

8. Shaker Sarwary (5 out of 5 patents)

9. Bhanu Kapoor (5 out of 5 patents)

10. Bernard Murphy (5 out of 6 patents)

11. Sridhar Gangadharan (4 out of 5 patents)

12. Ravi Varadarajan (4 out of 10 patents)

13. Debabrata Bagchi (4 out of 5 patents)

14. Paras Mal Jain (3 out of 13 patents)

15. Jitendra Kumar Gupta (3 out of 8 patents)

Core Competencies:

Assertion-Based Verification

Hybrid Clock Domain Crossing

Power Consumption Optimization

Circuit Design Hierarchy

Metastability Verification

Integrated Circuit Design

SoC Design Analysis

Clock Gating Techniques

Timing Exception Verification

Bus Contention Detection

Isolation Logic Modules

Physical Synthesis

47 patents: Sort by Forward Citations

1. 9135382 - Systems, methods, and media for assertion-based verification of devices (2015-09-15),

2. 8984469 - System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption (2015-03-17),

3. 8984457 - System and method for a hybrid clock domain crossing verification (2015-03-17),

4. 8930863 - System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist (2015-01-06),

5. 8881075 - Method for measuring assertion density in a system of verifying integrated circuit design (2014-11-04),

6. 8863058 - Characterization based buffering and sizing for system performance optimization (2014-10-14),

7. 8856706 - System and method for metastability verification of circuits of an integrated circuit (2014-10-07),

8. 8839171 - Method of global design closure at top level and driving of downstream implementation flow (2014-09-16),

9. 8813003 - System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency (2014-08-19),

10. 8806401 - System and methods for reasonable functional verification of an integrated circuit design (2014-08-12),

11. 8788993 - Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design (2014-07-22),

12. 8782587 - Systems and methods for generating a higher level description of a circuit design based on connectivity strengths (2014-07-15),

13. 8782582 - Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis (2014-07-15),

14. 8775989 - Computer-aided design system and methods thereof for merging design constraint files across operational modes (2014-07-08),

15. 8756466 - Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test (2014-06-17),

Atrenta, Inc. is a provider of electronic design automation (EDA) solutions for system-on-chip (SoC) and semiconductor companies. Their software tools and platforms help engineers optimize the performance and efficiency of their semiconductor designs. Atrenta's solutions enable faster time-to-market and reduce development costs by identifying potential design issues early in the design cycle. With a focus on automation, accuracy, and advanced analytics, Atrenta helps semiconductor companies deliver reliable and high-quality chips.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 30 2025

47 Patents

#183 in San Jose, CA

#1,712 in California

#7,185 in US

#14,401 in the World

San Jose, CA, United States of America

Atrenta, Inc.

Forward Citations = 279

69 inventors:

Mohammad Homayoun Movahed-Ezazi (11 out of 15 patents)

Solaiman Rahim (7 out of 19 patents)

Mohamed Shaker Sarwary (6 out of 12 patents)

4. Maher Mneimneh (5 out of 9 patents)

5. Anshuman Nayak (5 out of 6 patents)

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