The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2014
Filed:
Mar. 04, 2013
Atrenta, Inc., San Jose, CA (US);
Atrenta, Inc., San Jose, CA (US);
Abstract
An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.