For the Inventor, By the Inventor

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San Jose, CA, United States of America

Logicvision, Inc.

USPTO Granted Patents = 55

% Expired Patents = 12.7

Trademarks = 1

Forward Citations = 1,445

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38 inventors (with patents filed for the assignee):

Benoit Nadeau-Dostie (33 out of 49 patents)

Stephen Kenneth Sunter (19 out of 30 patents)

Jean-François Côté (7 out of 7 patents)

4. Jean-François Côté (6 out of 7 patents)

5. Aubin P J Roy (6 out of 6 patents)

6. Jean-Francois Cote (5 out of 5 patents)

7. Fadi Maamari (4 out of 13 patents)

8. Dwayne M Burek (3 out of 6 patents)

9. Sonny Ngai San Shum (3 out of 3 patents)

10. Paul Price (3 out of 3 patents)

11. Saman M I Adham (2 out of 31 patents)

12. Robert Abbott (2 out of 4 patents)

13. Luc Romain (2 out of 2 patents)

14. Jean-François Cote (2 out of 2 patents)

15. Pierre Gauthier (2 out of 2 patents)

Core Competencies:

Memory Interface

High Speed Signals

At-Speed Testing

Boundary Scan

Memory Repair

Circuit Diagnostics

Embedded Test Structures

Jitter Measurement

Fault Insertion

Digital Circuits

Analog Signals

Hierarchical Design

55 patents: Sort by Forward Citations

1. 7617425 - Method for at-speed testing of memory interface using scan (2009-11-10),

2. 7453255 - Circuit and method for measuring delay of high speed signals (2008-11-18),

3. 7424656 - Clocking methodology for at-speed testing of scan circuits with synchronous clocks (2008-09-09),

4. 7370251 - Method and circuit for collecting memory failure information (2008-05-06),

5. 7257733 - Memory repair circuit and method (2007-08-14),

6. 7219282 - Boundary scan with strobed pad driver enable (2007-05-15),

7. 7194669 - Method and circuit for at-speed testing of scan circuits (2007-03-20),

8. 7191374 - Method of and program product for performing gate-level diagnosis of failing vectors (2007-03-13),

9. 7188274 - Memory repair analysis method and circuit (2007-03-06),

10. 7159159 - Circuit and method for adding parametric test capability to digital boundary scan (2007-01-02),

11. 7158899 - Circuit and method for measuring jitter of high speed signals (2007-01-02),

12. 7155651 - Clock controller for at-speed testing of scan circuits (2006-12-26),

13. 7139946 - Method and test circuit for testing memory internal write enable (2006-11-21),

14. 7103860 - Verification of embedded test structures in circuit designs (2006-09-05),

15. 6961871 - Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data (2005-11-01),

Company Overview

Logicvision, Inc., based in San Jose, California, specializes in advanced memory testing technology. The company focuses on developing solutions that enhance the reliability and performance of memory interfaces through high-speed signals and at-speed testing methodologies. Their expertise extends to boundary scan techniques, memory repair, and circuit diagnostics, ensuring robust embedded test structures and precise jitter measurement. Logicvision's innovations support a wide range of applications in the semiconductor industry, contributing to the advancement of memory technology.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

55 Patents

#177 in San Jose, CA

#1,517 in California

#6,460 in US

#12,932 in the World

San Jose, CA, United States of America

Logicvision, Inc.

Forward Citations = 1,445

38 inventors:

Benoit Nadeau-Dostie (33 out of 49 patents)

Stephen Kenneth Sunter (19 out of 30 patents)

Jean-François Côté (7 out of 7 patents)

4. Jean-François Côté (6 out of 7 patents)

5. Aubin P J Roy (6 out of 6 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Logicvision, Inc.. Retrieved from https://idiyas.com/company/logicvision

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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