Synopsys, Inc.

Logicvision, Inc.

Atrenta, Inc.

Other

Fadi Maamari

Benoit Nadeau-Dostie

Emil I Gizdarski

Mohammad Homayoun Movahed-Ezazi

Suryanarayana Duggirala

Dwayne M Burek

Shaker Sarwary

Sridhar Gangadharan

Sonny Ngai San Shum

Apik A Zorian

Basim Mohammed Issa Shanyour

Mahilchi Milir Vaseekar Kumar

Jean-François Côté

Shivakumar Shankar Chonnad

Jean-Francois Cote

Jamileh Davoudi

Abhishek Chauhan

Subir Chandra Ray

Subir Subir Ray

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)

The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.

Scan chain formation for improving chain resolution

A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a corresponding node propagates to the observation point. The method further includes determining a weighted soft error probability for each logic element of the plurality of logic elements and determining a weighed soft error failure mode distribution for the cone of influence.

Automated determinaton of failure mode distribution

Training data may be collected based on a set of test-case configurations for each integrated circuit (IC) design in a set of IC designs. The training data may include a set of features extracted from each IC design, and a count of test cycles required for achieving a target test coverage for each test-case configuration. A machine learning (ML) model may be trained using the training data to obtain a trained ML model. The trained ML model may be used to predict a set of ranked test-case configurations for a given IC design based on features extracted from the given IC design.

Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR)

An integrated circuit (IC) design comprising a scan chain may be received, where stimulus values may be scanned-in and response values may be scanned-out through a scan path in the scan chain, where the scan path may include a first scan cell and a second scan cell such that the first scan cell is downstream with respect to the second scan cell. The scan chain may be modified to enable observation of a 0 and a 1 value in the first scan cell in presence of a defect in the second scan cell, or observation of a 0 and a 1 value in the second scan cell in presence of a defect in the first scan cell.

Integrated circuit design modification for localization of scan chain defects

In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.

Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design

In order to realize some of the advantages described above, there is provided a computer-implemented method for verification of an intellectual property (IP) core in a system-on-chip (SoC). The method comprises generating a plurality of verification specific abstracted views of the IP core each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.

Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design

A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.

Clocking methodology for at-speed testing of scan circuits with synchronous clocks

A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault candidate, the fault candidate diagnostic measure having a fault candidate match metric, an observed fault effect mismatch metric and a fault candidate excitation metric, ranking fault candidates in decreasing diagnostic measure order; and identifying fault candidate(s) having the highest diagnostic measure as the most likely cause of observed fault effects.

Method of and program product for performing gate-level diagnosis of failing vectors

A method and program product for verifying a logic design for proper operation of tri-state buses in the design, comprises, for each bus in the circuit design, determining the smallest cut set, a min-cut, of the logic controlling the bus, performing an exhaustive analysis on a min-cut set of logic, and performing a full exhaustive analysis of the bus when the exhaustive analysis on the min-cut set of logic is inconclusive. In a preferred embodiment, prior to performing the min-cut set analysis, implication based conflict-free and float-free analyses are performed on the bus.

Method and program product for detecting bus conflict and floating bus conditions in circuit designs

A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out. A test controller is clocked a test clock and includes a clock generation module for generating shift and capture clocks. The test clock can be an independent and asynchronous clock or derived from the system clock. The test can also be performed by using only the test clock in the case only the test clock is available or for diagnostic and debug purposes.

Method and apparatus for testing high performance circuits

A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.

Growing community of inventors

San Jose, CA, United States of America

Fadi Maamari