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For the Inventor, By the Inventor

Peekskill, NY, United States of America

Claude Ortolland

This inventor holds 29 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Technology. Top assignees: International Business Machines Corporation, Globalfoundries Inc., Globalfoundries U.S. Inc.. Active years: 2015-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Claude Ortolland. Retrieved from https://idiyas.com/inventor/claude-ortolland

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 29 

% Patents Active = 86.2

Average Co-Inventor Count = 5.3

ph-index = 7

Forward Citations = 122(Granted Patents)


Location History:

  • Hopewell Junction, NY (US) (2018)
  • Peekskill, NY (US) (2015 - 2021)
  • Garrison, NY (US) (2018 - 2022)
  • Austin, TX (US) (2022)

Company Filing History:

goldMedal17 out of 166,524 
 
International Business Machines Corporation
 patents
silverMedal6 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal3 out of 1,107 
 
Globalfoundries U.S. Inc.
 patents
4. 2 out of 1,916 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
5. 1 out of 834,708 
Other
 patents

Years Active: 2015-2022

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Areas of Expertise:
Semiconductor
Heterojunction Bipolar Transistor
High-K Dielectric
Gate Leakage
Nanotube Structures
Field-Effect Transistors
Epitaxial Material
Buffer Layer
Oxygen Permeable Layer
Morphology Modulation
Metal Semiconductor Alloy
Dielectric Metallic Oxide
29 patents (USPTO):Explore Patents
1. 11374092 - Virtual bulk in semiconductor on insulator technology (2022-06-28),
2. 11217685 - Heterojunction bipolar transistor with marker layer (2022-01-04),
3. 11145725 - Heterojunction bipolar transistor (2021-10-12),
4. 11101357 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2021-08-24),
5. 10734492 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2020-08-04),
6. 10381452 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-08-13),
7. 10374048 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-08-06),
8. 10367072 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-07-30),
9. 10170304 - Self-aligned nanotube structures (2019-01-01),
10. 9953873 - Methods of modulating the morphology of epitaxial semiconductor material (2018-04-24),
11. 9922831 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2018-03-20),
12. 9871057 - Field-effect transistors with a non-relaxed strained channel (2018-01-16),
13. 9859122 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2018-01-02),
14. 9837319 - Asymmetric high-K dielectric for reducing gate induced drain leakage (2017-12-05),
15. 9831084 - Hydroxyl group termination for nucleation of a dielectric metallic oxide (2017-11-28),

Title: Claude Ortolland: A Trailblazer in Technological Advancement

Introduction:

Claude Ortolland, a visionary inventor hailing from Peekskill, NY, is a beacon of inspiration in the realm of technological innovation. With an impressive portfolio of 29 patents to his name, Ortolland's dedication to pushing the boundaries of semiconductor technology has left an indelible mark on the industry.

Latest Patents:

1. Virtual bulk in semiconductor on insulator technology: Ortolland's pioneering work in semiconductor structures introduces a novel approach to virtual bulk in semiconductor on insulator technology, revolutionizing the field.

2. Heterojunction bipolar transistor with marker layer: By incorporating a marker layer into semiconductor structures, Ortolland's invention enhances the performance and efficiency of devices, setting new standards in the industry.

Career Highlights:

Having contributed significantly to leading companies such as IBM and Globalfoundries Inc., Ortolland's expertise and innovative spirit have been instrumental in driving technological advancements. His relentless pursuit of excellence has garnered widespread recognition and respect within the tech community.

Collaborations:

Ortolland's collaborative efforts with esteemed colleagues like Arvind Kumar and Shreesh Narasimha have led to groundbreaking innovations and groundbreaking solutions in semiconductor technology. Through teamwork and shared expertise, Ortolland has elevated the standards of innovation in the field.

Conclusion:

Claude Ortolland's unparalleled passion for innovation and unwavering commitment to technological advancement serve as a testament to his enduring legacy. His contributions continue to inspire the next generation of inventors, shaping the future of technology in profound ways.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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