The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2018
Filed:
Mar. 03, 2016
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Karen A. Nummy, Hopewell Junction, NY (US);
Claude Ortolland, Hopewell Junction, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 27/12 (2006.01); H01L 31/0392 (2006.01); H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 27/092 (2006.01); H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01);
Abstract
Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.