International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Adeia Semiconductor Bonding Technologies Inc.

Other

Claude Ortolland

Arvind Kumar

Shreesh Narasimha

Chung-Hsun Lin

Anthony I Chou

Jonathan T Shaw

Martin Michael Frank

Takashi Ando

Qizhi Liu

Judson Robert Holt

Vibhor Jain

Herbert Lei Ho

John Joseph Pekarik

Viorel C Ontalus

Cyril Cabral, Jr

Michael Patrick Chudzik

Barry P Linder

Paul S Chang

Rishikesh Krishnan

Nicolas L Breil

Joseph Francis Shepard, Jr

Timothy James McArdle

Min Dai

Bhupesh Chandra

Kai Zhao

David F Hilscher

Dominic Joseph Schepis

Gregory Gower Freeman

Karen A Nummy

Oh-Jung Kwon

Christopher D Sheraw

Christopher N Collins

Anthony I-Chih Chou

The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

Virtual bulk in semiconductor on insulator technology

The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

Heterojunction bipolar transistor with marker layer

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

Heterojunction bipolar transistor

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Asymmetric high-k dielectric for reducing gate induced drain leakage

The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.

Self-aligned nanotube structures

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Methods of modulating the morphology of epitaxial semiconductor material

Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

Field-effect transistors with a non-relaxed strained channel

Asymmetric high-K dielectric for reducing gate induced drain leakage

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Hydroxyl group termination for nucleation of a dielectric metallic oxide

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Peekskill, NY, United States of America

Claude Ortolland