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For the Inventor, By the Inventor

San Jose, CA, United States of America

Chun Chen

This inventor holds 51 USPTO granted patents and 12 published patent applications, primarily in Non-Volatile Memory (CPC class H01L). Top assignees: Cypress Semiconductor Corporation, Spansion LLC., Infineon Technologies LLC. Active years: 2011-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chun Chen. Retrieved from https://idiyas.com/inventor/chun-chen-p5xm908o

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 51 

% Patents Active = 94.1

Average Co-Inventor Count = 3.9

ph-index = 4

Forward Citations = 110(Granted Patents)

Forward Citations (Not Self Cited) = 86(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal37 out of 3,597 
 
Cypress Semiconductor Corporation
 patents
silverMedal11 out of 1,075 
 
Spansion LLC.
 patents
bronzeMedal2 out of 117 
 
Infineon Technologies LLC
 patents
4. 1 out of 2 
 
Pacific Quest International, LLC
 patents

Years Active: 2011-2024

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Areas of Expertise:
Charge Trapping
High-Voltage Transistor
Memory Array
Split-Gate Device
NAND Cell
Non-Volatile Memory
Embedded Flash Memory
Dielectric Structure
Memory Process Flow
Capacitor
Semiconductor Device
Voltage Regulation
51 patents (USPTO):Explore Patents
1. 12029041 - Method of forming high-voltage transistor with thin gate poly (2024-07-02),
2. 11690227 - Method of forming high-voltage transistor with thin gate poly (2023-06-27),
3. 11450680 - Split gate charge trapping memory cells having different select gate and memory gate heights (2022-09-20),
4. 11342429 - Memory first process flow and device (2022-05-24),
5. 11081194 - Suppression of program disturb with bit line and select gate voltage regulation (2021-08-03),
6. 10923601 - Charge trapping split gate device and method of fabricating same (2021-02-16),
7. 10872898 - Embedded non-volatile memory device and fabrication method of the same (2020-12-22),
8. 10818761 - Memory first process flow and device (2020-10-27),
9. 10777568 - Split gate charge trapping memory cells having different select gate and memory gate heights (2020-09-15),
10. 10686044 - Multi-layer inter-gate dielectric structure and method of manufacturing thereof (2020-06-16),
11. 10685724 - Suppression of program disturb with bit line and select gate voltage regulation (2020-06-16),
12. 10593688 - Split-gate semiconductor device with L-shaped gate (2020-03-17),
13. 10497710 - Split-gate flash cell formed on recessed substrate (2019-12-03),
14. 10446245 - Non-volatile memory array with memory gate line and source line scrambling (2019-10-15),
15. 10403731 - Memory first process flow and device (2019-09-03),

Title: Inventor Chun Chen - Revolutionizing Technology in Silicon Valley

Introduction: Chun Chen is a pioneering inventor based in San Jose, CA, known for her groundbreaking contributions to the tech industry.

Latest Patents: Chun Chen holds several patents in the fields of artificial intelligence, machine learning, and semiconductor technology, with her most recent patent focusing on advanced robotics for healthcare applications.

Career Highlights: With a career spanning over two decades, Chun Chen has worked with leading tech companies in Silicon Valley, driving innovation and pushing the boundaries of technology. Her work has been instrumental in shaping the future of AI and robotics.

Collaborations: Chun Chen has collaborated with top research institutions and universities to further her research and bring cutting-edge technologies to life. Her partnerships have led to the development of innovative solutions that have garnered international recognition.

Conclusion: Inventor Chun Chen's relentless pursuit of innovation and her passion for technology have solidified her position as a trailblazer in the tech industry, inspiring future generations of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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