The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Feb. 10, 2017
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 27/11568 (2017.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 27/105 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/1052 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract
A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.