The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Sep. 08, 2020
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Chun Chen, San Jose, CA (US);

Mark Ramsbey, Sunnyvale, CA (US);

Shenqing Fang, Sunnyvale, CA (US);

Assignee:

Infineon Technologies LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 27/11568 (2017.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 27/105 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/1052 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.


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