The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2020
Filed:
Dec. 20, 2017
Cypress Semiconductor Corporation, San Jose, CA (US);
Chun Chen, San Jose, CA (US);
James Pak, Sunnyvale, CA (US);
Unsoon Kim, San Jose, CA (US);
Inkuk Kang, San Jose, CA (US);
Sung-Taeg Kang, Palo Alto, CA (US);
Kuo Tung Chang, Saratoga, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.