Choong Kooi Chee

This inventor holds 26 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Packaging. Top assignees: Intel Corporation, Altera Corporation. Active years: 2004-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Choong Kooi Chee. Retrieved from https://idiyas.com/inventor/choong-kooi-chee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 26 (Patent Applications = 4)

% Patents Active = 65.4

Average Co-Inventor Count = 2.3

ph-index = 5

Forward Citations = 49(Granted Patents)

Location History:

Balik Pulau, MY (2015 - 2018)
Georgetown, MY (2018)
Penang, MY (2004 - 2023)
Pulau Pinang, MY (2022 - 2023)
Gelugor, MY (2023 - 2024)

Company Filing History:

Years Active: 2004-2025

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Areas of Expertise:

Through-Silicon Via

Multi-Chip Assembly

Microelectronic Devices

Stacked Packages

Interconnect Bridges

Embedded Die

Molded Matrix Array

Capillary Underfill

MEMS Pump

Redistribution Layer

Thermal Management

Stress-Compensation Layers

26 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12237245 - Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same (2025-02-25),

2. 12125768 - Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same (2024-10-22),

3. 12112997 - Micro through-silicon via for transistor density scaling (2024-10-08),

4. 12080628 - Micro through-silicon via for transistor density scaling (2024-09-03),

5. 11805602 - Chip assemblies (2023-10-31),

6. 11652026 - Micro through-silicon via for transistor density scaling (2023-05-16),

7. 11562959 - Embedded dual-sided interconnect bridges for integrated-circuit packages (2023-01-24),

8. 11527481 - Stacked semiconductor package with flyover bridge (2022-12-13),

9. 11398415 - Stacked through-silicon vias for multi-device packages (2022-07-26),

10. 11393741 - Micro through-silicon via for transistor density scaling (2022-07-19),

11. 11107751 - Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same (2021-08-31),

12. 10903142 - Micro through-silicon via for transistor density scaling (2021-01-26),

13. 10136516 - Microelectronic device attachment on a reverse microelectronic package (2018-11-20),

14. 9978735 - Interconnection of an embedded die (2018-05-22),

15. 9699904 - Microelectronic device attachment on a reverse microelectronic package (2017-07-04),

Title: The Innovator Extraordinaire: Choong Kooi Chee

Introduction: Choong Kooi Chee, a visionary inventor hailing from Penang, Malaysia, has left an indelible mark on the world of technology through his groundbreaking innovations and unwavering commitment to excellence.

Latest Patents: Choong Kooi Chee's latest patents showcase his expertise in chip assemblies and micro through-silicon via for transistor density scaling, revolutionizing the way electronic devices are designed and manufactured.

Career Highlights: With a remarkable portfolio of 22 patents, Choong Kooi Chee has made significant contributions during his tenure at renowned companies such as Intel Corporation and Altera Corporation, where his inventive genius has reshaped the landscape of technological advancements.

Collaborations: Throughout his illustrious career, Choong Kooi Chee has collaborated with esteemed professionals in the field, including Bok Eng Cheah and Jackson Chung Peng Kong, fostering a culture of innovation and collective success.

Conclusion: Choong Kooi Chee's relentless pursuit of innovation and his trailblazing spirit serve as a source of inspiration for future generations of inventors, propelling us towards a brighter and more innovative tomorrow.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

4 patents pending: