The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Nov. 06, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Choong Kooi Chee, Pulau Pinang, MY;

Bok Eng Cheah, Pinang, MY;

Teong Guan Yew, Pulau Pinang, MY;

Jackson Chung Peng Kong, Pinang, MY;

Loke Yip Foo, Pinang, MY;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 25/18 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 23/13 (2013.01); H01L 23/3107 (2013.01); H01L 23/5389 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01);
Abstract

According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.


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