The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

May. 03, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bok Eng Cheah, Bukit Gambir, MY;

Choong Kooi Chee, Penang, MY;

Jackson Chung Peng Kong, Tanjung Tokong, MY;

Tat Hin Tan, Bayan Lepas, MY;

Wai Ling Lee, Bayan Lepas, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/48 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 21/8221 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/16 (2013.01); H01L 28/40 (2013.01);
Abstract

An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.


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