The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Jun. 25, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Loke Yip Foo, Bayan Baru, MY;

Teong Guan Yew, Bagan Serai, MY;

Choong Kooi Chee, Penang, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01);
Abstract

A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.


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