The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Dec. 27, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Loke Yip Foo, Bayan Baru, MY;
Choong Kooi Chee, Penang, MY;
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/3672 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 24/97 (2013.01); H01L 25/18 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01);
Abstract
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.