logo

For the Inventor, By the Inventor

Cupertino, CA, United States of America

Chok J Chia

This inventor holds 73 USPTO granted patents and 1 EPO patent, primarily in 3D Interconnects (CPC class H01L). Top assignees: Lsi Logic Corporation, Adeia Semiconductor Bonding Technologies Inc., National Semiconductor Corporation. Active years: 1987-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chok J Chia. Retrieved from https://idiyas.com/inventor/chok-j-chia

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 73

% Patents Active = 91.8


Average Co-Inventor Count = 2.7

ph-index = 20

Forward Citations = 1,595(Granted Patents)

Forward Citations (Not Self Cited) = 1,557(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Santa Clara, CA (US) (1987 - 1989)
  • Capertino, CA (US) (2000)
  • Campbell, CA (US) (1993 - 2001)
  • Cupertino, CA (US) (1998 - 2024)

Company Filing History:

goldMedal57 out of 3,715 
 
Lsi Logic Corporation
 patents
silverMedal8 out of 1,916 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
bronzeMedal5 out of 4,791 
 
National Semiconductor Corporation
 patents
4. 1 out of 33 
 
Adeia Semiconductor Technologies LLC
 patents
5. 1 out of 2,353 
 
Lsi Corporation
 patents
6. 1 out of 834,708 
Other
 patents

Years Active: 1987-2025

Loading Chart...
Loading Chart...
Areas of Expertise:
3D Interconnect
Semiconductor Packaging
Ball Grid Array
Quad Flat No-Lead
Flip-Chip Structure
Integrated Circuit Package
Hybrid High Density
Microelectronic Packaging
Thermal Management
Solder Ball Planarization
Anodized Aluminum Heatspreader
Electrostatic Protected Substrate
73 patents (USPTO):Explore Patents
1. 12476212 - 3D-interconnect (2025-11-18),
2. 11929337 - 3D-interconnect (2024-03-12),
3. 11031362 - 3D-interconnect (2021-06-08),
4. 10181447 - 3D-interconnect (2019-01-15),
5. 9875955 - Low cost hybrid high density package (2018-01-23),
6. 9508687 - Low cost hybrid high density package (2016-11-29),
7. 8963310 - Low cost hybrid high density package (2015-02-24),
8. 8525312 - Area array quad flat no-lead (QFN) package (2013-09-03),
9. 8525309 - Flip-chip QFN structure using etched lead frame (2013-09-03),
10. 8129759 - [object Object] (2012-03-06),
11. 7804167 - Wire bond integrated circuit package for high speed I/O (2010-09-28),
12. 7646091 - [object Object] (2010-01-12),
13. 7327043 - Two layer substrate ball grid array design (2008-02-05),
14. 6991147 - Insulated bonding wire tool for microelectronic packaging (2006-01-31),
15. 6963138 - Dielectric stack (2005-11-08),

Title: The Innovative Journey of Chok J Chia

Introduction: Chok J Chia, a visionary inventor based in Cupertino, CA, has made significant contributions to the world of technology through his groundbreaking innovations.

Latest Patents: Chok J Chia holds several patents in the field of artificial intelligence and renewable energy technologies, showcasing his commitment to creating a sustainable future.

Career Highlights: With a background in engineering and a passion for problem-solving, Chok J Chia has led successful projects that have revolutionized industries and improved the lives of many.

Collaborations: Throughout his career, Chok J Chia has collaborated with leading tech companies and research institutions to bring his ideas to life, fostering a culture of innovation and creativity.

Conclusion: Chok J Chia's dedication to pushing the boundaries of what is possible through his inventions has solidified his reputation as a pioneering figure in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…