Kaohsiung, Taiwan

Chao-Yuan Su

This inventor holds 30 USPTO granted patents, primarily in Semiconductor Packaging. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2003-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chao-Yuan Su. Retrieved from https://idiyas.com/inventor/chao-yuan-su

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0

Average Co-Inventor Count = 2.5

ph-index = 11

Forward Citations = 315(Granted Patents)


Location History:

  • Koashiung, TW (2003)
  • Koahsiang, TW (2004)
  • Baoshan Township, Hsinchu County, TW (2007)
  • Kaohsiung, TW (2004 - 2013)
  • Koahsiung, TW (2004 - 2014)
  • Hsin-Chu, TW (2003 - 2017)

Company Filing History:


Years Active: 2003-2017

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Areas of Expertise:
Stress-Sensitive Circuit Design
Through-Silicon Vias
Flip Chip Reliability
Bump Reliability
Wafer-Level Packaging
Microelectronics Assembly
Solder Ball Formation
Cathodic Protection
Delamination Reduction
Stencil Design
Fluxless Bumping Process
Substrate Design
30 patents (USPTO):Explore Patents

Title: The Innovations of Chao-Yuan Su in Semiconductor Design

Introduction

Chao-Yuan Su is a prominent inventor situated in Kaohsiung, Taiwan, renowned for his significant contributions to the field of semiconductor design. With an impressive portfolio of 30 patents, Chao-Yuan has made strides in innovations that enhance the performance and reliability of semiconductor structures.

Latest Patents

Chao-Yuan Su's latest patent focuses on an exclusion zone for stress-sensitive circuit design. This innovative semiconductor structure is designed to be less affected by stress, thus improving the functionality of stress-sensitive circuits. The unique layout of the semiconductor structure incorporates an exclusion zone, smartly placing stress-sensitive circuits away from areas of potential stress impact. This design notably focuses on corner regions of the semiconductor chip that have a diagonal length of less than one percent of the chip's diagonal length. The patent emphasizes that the stress-sensitive analog circuits contain devices with channel lengths smaller than five times the minimum channel length, further enhancing the efficacy of these circuits in high-performance applications.

Career Highlights

Chao-Yuan Su is currently affiliated with Taiwan Semiconductor Manufacturing Company, a leading entity in the semiconductor industry. His work has not only contributed to the company's innovations but has also established him as an influential figure in semiconductor research. His dedication to refining circuit design has marked significant advancements in the sector.

Collaborations

During his career, Chao-Yuan has collaborated with talented coworkers such as Hsin-Hui Lee and Chia-Fu Lin. Together, they have pushed the boundaries of semiconductor technology, contributing to the growth and sustainability of innovative designs within the industry.

Conclusion

Chao-Yuan Su's innovative work in semiconductor design exemplifies the ingenuity and potential within the field of electronics. His latest patent demonstrates a forward-thinking approach to addressing challenges faced by stress-sensitive circuits, further solidifying his reputation as a leading inventor in the semiconductor landscape. As the industry continues to evolve, the advancements driven by inventors like Chao-Yuan will undoubtedly pave the way for a more efficient and reliable technological future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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