The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Dec. 04, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chao-Yuan Su, Hsin-Chu, TW;

Chung-Yi Lin, Hsin-chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/29 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0203 (2013.01);
Abstract

A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.


Find Patent Forward Citations

Su, Chao-Yuan. (2014). Exclusion zone for stress-sensitive circuit design (U.S. Patent No. 8829653). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8829653

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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