The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2007
Filed:
Jul. 28, 2006
Chao-yuan Su, Koahsiung, TW;
Pei-haw Tsao, Tai-Chung, TW;
Hsin-hui Lee, Koahsiung, TW;
Chender Huang, Hsin-Chu, TW;
Shang Y. Hou, Hsin-Chu, TW;
Shin Puu Jeng, Hsin-Chu, TW;
Hao-yi Tsai, Hsin-Chu, TW;
Chenming HU, Hsin-Chu, TW;
Chao-Yuan Su, Koahsiung, TW;
Pei-Haw Tsao, Tai-Chung, TW;
Hsin-Hui Lee, Koahsiung, TW;
Chender Huang, Hsin-Chu, TW;
Shang Y. Hou, Hsin-Chu, TW;
Shin Puu Jeng, Hsin-Chu, TW;
Hao-Yi Tsai, Hsin-Chu, TW;
Chenming Hu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area Ais defined on the first scribe line and is defined by the equation A=D×S, where Dis the distance from the corner point of the die toward the main area of the die, and Sis the width of the first scribe line. Free area Ais defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation A=S×S, where Sis the width of the second scribe line.