For the Inventor, By the Inventor

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San Jose, CA, United States of America

Silicon Storage Technology, Inc.

Calculating rank

USPTO Granted Patents = 658

% Expired Patents = 1.7

EPO Patents = 218

Trademarks = 2

Forward Citations = 7,291

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264 inventors (with patents filed for the assignee):

Hieu Van Tran (311 out of 328 patents)

Nhan Do (196 out of 196 patents)

Thuan Vu (123 out of 131 patents)

4. Anh Ly (119 out of 120 patents)

5. Vipin Tiwari (100 out of 106 patents)

6. Hung Quoc Nguyen (96 out of 96 patents)

7. Xian Liu (65 out of 75 patents)

8. Stanley Hong (62 out of 114 patents)

9. Mark Reiten (55 out of 55 patents)

10. Bomy A Chen (49 out of 97 patents)

11. Steven Lemke (46 out of 46 patents)

12. Sang Thanh Nguyen (44 out of 71 patents)

13. Stephen Trinh (43 out of 56 patents)

14. Dana Lee (38 out of 133 patents)

15. Chien-Sheng Su (33 out of 36 patents)

Core Competencies:

Non-Volatile Memory Cells

Split-Gate Technology

Redundancy Techniques

Neural Networks

Analog Memory

Charge Pump

Bias Voltage

Programming Methods

Error Correction

Deep Learning

Data Tuning

High Voltage Devices

658 patents: Sort by Forward Citations

1. 12795909 - Method of making memory cells, transistor devices and logic devices on silicon-on-insulator substrate (2026-11-10),

2. 12793791 - Dual read mode non-volatile memory semiconductor device (2026-11-10),

3. 12792900 - Split array architecture for analog neural memory in a deep learning artificial neural network (2026-11-10),

4. 12755788 - Address fault detection in a memory system (2026-10-06),

5. 12738325 - Sequential erase for tuning the program state of non-volatile memory cells (2026-09-15),

6. 12738323 - Programming method for non-volatile memory cells (2026-09-15),

7. 12727159 - Non-volatile memory cell with ONO compound insulation layer between floating and control gates and a method of fabrication (2026-09-01),

8. 12724562 - Masking sparse inputs and outputs in neural network array (2026-09-01),

9. 12718080 - Calibration of electrical parameters in a deep learning artificial neural network (2026-08-25),

10. 12699890 - Word line driver for vector-by-matrix multiplication array (2026-08-04),

11. 12699889 - Output circuitry for analog neural memory in a deep learning artificial neural network (2026-08-04),

12. 12694279 - Precision tuning for the programming of analog neural memory in a deep learning artificial neural network (2026-07-28),

13. 12694070 - Verification method and system in artificial neural network array (2026-07-28),

14. 12670377 - Adjustable programming circuit for neural network (2026-06-30),

15. 12670376 - Testing circuitry and methods for analog neural memory in artificial neural network (2026-06-30),

Company Overview

Silicon Storage Technology, Inc. is a leading innovator in the field of non-volatile memory solutions, headquartered in San Jose, California. The company specializes in the development and manufacturing of advanced memory technologies, including non-volatile memory cells and split-gate technology. SST's expertise extends to redundancy techniques, neural networks, and analog memory, enabling robust data storage solutions. Their focus on charge pump and bias voltage programming methods positions them at the forefront of memory technology advancements.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Nov 10 2026

658 Patents

#33 in San Jose, CA

#173 in California

#767 in US

#1,516 in the World

San Jose, CA, United States of America

Silicon Storage Technology, Inc.

Forward Citations = 7,291

264 inventors:

Hieu Van Tran (311 out of 328 patents)

Nhan Do (196 out of 196 patents)

Thuan Vu (123 out of 131 patents)

4. Anh Ly (119 out of 120 patents)

5. Vipin Tiwari (100 out of 106 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Silicon Storage Technology, Inc.. Retrieved from https://idiyas.com/company/silicon-storage-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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