The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Nov. 27, 2023
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hieu Van Tran, San Jose, CA (US);

Stanley Hong, San Jose, CA (US);

Anh Ly, San Jose, CA (US);

Thuan Vu, San Jose, CA (US);

Hien Pham, Ho Chi Minh, VN;

Kha Nguyen, Ho Chi Minh, VN;

Han Tran, Ho Chi Minh, VN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G11C 11/54 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G11C 11/54 (2013.01); G11C 16/0408 (2013.01);
Abstract

In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.


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