The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Jul. 27, 2022
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hieu Van Tran, San Jose, CA (US);

Steven Lemke, Boulder Creek, CA (US);

Vipin Tiwari, Dublin, CA (US);

Nhan Do, Saratoga, CA (US);

Mark Reiten, Alamo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/54 (2006.01); G06F 17/16 (2006.01); G06N 3/065 (2023.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 17/16 (2013.01); G11C 11/54 (2013.01); G11C 11/5628 (2013.01);
Abstract

Numerous examples of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a method for performing a read or verify operation in a vector-by-matrix multiplication system comprising an input function circuit, a memory array, and an output circuit block is disclosed, the method comprising receiving, by the input function circuit, digital bit input values; converting the digital input values into an input signal; applying the input signal to control gate terminals of selected cells in the memory array; and generating, by the output circuit block, an output value in response to currents received from the memory array.


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