The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Jun. 04, 2024
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Steven Lemke, Boulder Creek, CA (US);

Gilles Festes, Fuveau, FR;

Louisa Schneider, San Jose, CA (US);

Yuri Tkachev, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/16 (2013.01);
Abstract

A method and device for erasing a memory cell with a floating gate, by applying successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current, and then applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved. The first erase pulses include a first parameter following a first progression that changes in value after respective ones of the first erase pulses. The first progression begins with a first value and ends with a second value. The second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses. The second progression begins with a third value that is between, and unequal to, the first and second values.


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