The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jan. 28, 2022
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventor:

Hieu Van Tran, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 16/0425 (2013.01); G11C 16/26 (2013.01); H10B 41/30 (2023.02);
Abstract

Various examples of memory systems comprising an address fault detection system are disclosed. The memory system comprises a first memory array, a row decoder, and an address fault detection system comprising a second array, wherein the row decoder decodes row addresses into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array. The second array contains digital bits and/or analog values that are used to identify address faults.


Find Patent Forward Citations

Tran, Hieu. (2026). Address fault detection in a memory system (U.S. Patent No. 12755788). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12755788

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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