The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Jun. 20, 2023
Applicant:
Silicon Storage Technology, Inc., San Jose, CA (US);
Inventors:
Hieu Van Tran, San Jose, CA (US);
Stephen Trinh, San Jose, CA (US);
Hoa Vu, Milpitas, CA (US);
Stanley Hong, San Jose, CA (US);
Thuan Vu, San Jose, CA (US);
Assignee:
Silicon Storage Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0655 (2013.01); G06F 3/062 (2013.01); G06F 3/0679 (2013.01); G11C 16/08 (2013.01);
Abstract
Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.