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Los Gatos, CA, United States of America

Atomera Incorporated

USPTO Granted Patents = 114

EPO Patents = 26

Trademarks = 3

Forward Citations = 3,036

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22 inventors (with patents filed for the assignee):

Hideki Takeuchi (57 out of 61 patents)

Robert J Mears (56 out of 93 patents)

Marek Hytha (47 out of 70 patents)

4. Nyles Wynn Cody (36 out of 51 patents)

5. Richard Burton (33 out of 40 patents)

6. Keith Doran Weeks (28 out of 44 patents)

7. Robert John Stephenson (25 out of 41 patents)

8. Daniel J Connelly (13 out of 53 patents)

9. Yi-Ann Chen (12 out of 13 patents)

10. Abid Husain (9 out of 10 patents)

11. Yung-Hsuan Yang (7 out of 7 patents)

12. Erwin Trautmann (6 out of 7 patents)

13. Richard Stephen Roy (6 out of 61 patents)

14. Dmitri Choutov (5 out of 8 patents)

15. Kalipatnam Vivek Rao (3 out of 12 patents)

Core Competencies:

Superlattice

Semiconductor

Bipolar Junction Transistors

RF Devices

Gate-All-Around

FINFET

Image Sensors

Contact Resistance

Memory Devices

Nanostructure Transistors

Defect Densities

Vertical Integration

114 patents: Sort by Forward Citations

1. 12765335 - Method for making radio frequency silicon-on-insulator (RFSOI) structure including a superlattice (2026-10-13),

2. 12712011 - Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers And Methods For Operating Same (2026-08-18),

3. 12707690 - Gate-all-around (GAA) device including a superlattice (2026-08-11),

4. 12635271 - Method for making image sensor devices including a superlattice (2026-05-19),

5. 12635155 - Methods for making bipolar junction transistors including emitter-base and base-collector superlattices (2026-05-19),

6. 12635122 - Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operating same (2026-05-19),

7. 12575199 - Image sensor devices including a superlattice (2026-03-10),

8. 12477798 - Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer (2025-11-18),

9. 12439658 - Semiconductor device including a superlattice providing metal work function tuning (2025-10-07),

10. 12439618 - Bipolar junction transistors including emitter-base and base-collector superlattices (2025-10-07),

11. 12417912 - Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice (2025-09-16),

12. 12382689 - Method for making DMOS devices including a superlattice and field plate for drift region diffusion (2025-08-05),

13. 12322594 - Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer (2025-06-03),

14. 12315723 - Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms (2025-05-27),

15. 12315722 - Method for making a radio frequency silicon-on-insulator (RFSOI) wafer including a superlattice (2025-05-27),

Company Overview

Atomera Incorporated, based in Los Gatos, California, specializes in advanced semiconductor technologies. The company focuses on developing innovative solutions in the semiconductor field, particularly in areas such as superlattice structures, bipolar junction transistors, and RF devices. Atomera's core technologies also encompass Gate-All-Around and FINFET architectures, as well as image sensors and contact resistance improvements. Their research aims to enhance device performance and efficiency, addressing the evolving demands of the semiconductor industry.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

114 Patents

#3 in Los Gatos, CA

#762 in California

#3,370 in US

#6,950 in the World

Los Gatos, CA, United States of America

Atomera Incorporated

Forward Citations = 3,036

22 inventors:

Hideki Takeuchi (57 out of 61 patents)

Robert J Mears (56 out of 93 patents)

Marek Hytha (47 out of 70 patents)

4. Nyles Wynn Cody (36 out of 51 patents)

5. Richard Burton (33 out of 40 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Atomera Incorporated. Retrieved from https://idiyas.com/company/atomera

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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