The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Jun. 20, 2024
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Marek Hytha, Brookline, MA (US);

Keith Doran Weeks, Chandler, AZ (US);

Nyles Wynn Cody, Tempe, AZ (US);

Hideki Takeuchi, San Jose, CA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 21/02507 (2013.01); H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H10D 84/0126 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.


Find Patent Forward Citations

Loading…