The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

May. 20, 2024
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Hideki Takeuchi, San Jose, CA (US);

Robert J. Mears, Wellesley, MA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H10D 30/60 (2025.01); H10D 30/69 (2025.01); H10D 62/815 (2025.01);
U.S. Cl.
CPC ...
H01L 21/02507 (2013.01); H01L 21/0245 (2013.01); H10D 30/601 (2025.01); H10D 30/751 (2025.01); H10D 62/8164 (2025.01);
Abstract

A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.


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