The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Nov. 14, 2023
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventor:

Richard Stephen Roy, Lago Vista, TX (US);

Assignee:

Atomera Incorporated, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/4096 (2006.01); H10B 80/00 (2023.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10B 12/033 (2023.02); G11C 11/4096 (2013.01); H10B 12/50 (2023.02); H10B 80/00 (2023.02); H10W 90/00 (2026.01);
Abstract

A memory system including a first chip having a processor, and a second chip having a DRAM sector that includes: a plurality of DRAM arrays; an output circuit configured to store a plurality of data values read from the DRAM arrays; a first set of through silicon vias (TSVs) connecting the processor to the DRAM sector, wherein the first processor transmits a plurality of weight data values to the DRAM sector on the first set of TSVs; a plurality of comparator arrays coupled to receive the plurality of weight data values and the plurality of data values read from the DRAM arrays, and in response, generate a plurality of comparison output values; and a second set of TSVs connecting the processor to the DRAM sector, wherein the plurality of comparison output values are transmitted from DRAM sector to the processor on the second set of TSVs.


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