The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
Apr. 30, 2015
Invensas Corporation, San Jose, CA (US);
Rajesh Katkar, San Jose, CA (US);
Tu Tam Vu, San Jose, CA (US);
Bongsub Lee, Mountain View, CA (US);
Kyong-Mo Bang, Fremont, CA (US);
Xuan Li, Santa Clara, CA (US);
Long Huynh, Santa Clara, CA (US);
Gabriel Z. Guevara, San Jose, CA (US);
Akash Agrawal, San Jose, CA (US);
Willmar Subido, Garland, TX (US);
Laura Wills Mirkarimi, Sunol, CA (US);
Invensas Corporation, San Jose, CA (US);
Abstract
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out ('FO') region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.