The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2025
Filed:
May. 15, 2024
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Shang-Yun Hou, Jubei, TW;
Sung-Hui Huang, Dongshan Township, TW;
Kuan-Yu Huang, Taipei, TW;
Hsien-Pin Hu, Zhubei, TW;
Yushun Lin, Taipei, TW;
Heh-Chang Huang, Hsinchu, TW;
Hsing-Kuo Hsia, Jhubei, TW;
Chih-Chieh Hung, Hsinchu, TW;
Ying-Ching Shih, Hsinchu, TW;
Chin-Fu Kao, Taipei, TW;
Wen-Hsin Wei, Hsinchu, TW;
Li-Chung Kuo, Taipei, TW;
Chi-Hsi Wu, Hsinchu, TW;
Chen-Hua Yu, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.