The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2020
Filed:
Jan. 31, 2020
Tessera, Inc., San Jose, CA (US);
Hiroaki Sato, Yokohama, JP;
Teck-Gyu Kang, San Jose, CA (US);
Belgacem Haba, Saratoga, CA (US);
Philip R. Osborn, San Jose, CA (US);
Wei-Shun Wang, Palo Alto, CA (US);
Ellis Chau, San Jose, CA (US);
Ilyas Mohammed, Santa Clara, CA (US);
Norihito Masuda, Yokohama, JP;
Kazuo Sakuma, Iwaki, JP;
Kiyoaki Hashimoto, Kanagawa, JP;
Kurosawa Inetaro, Kanagawa, JP;
Tomoyuki Kikuchi, Kanagawa, JP;
Tessera, Inc., San Jose, CA (US);
Abstract
Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.