San Jose, CA, United States of America

Zhiyuan Wu

This inventor holds 26 USPTO granted patents and 20 published patent applications and 2 EPO patents, primarily in Semiconductor Manufacturing. Top assignees: Applied Materials, Inc., Xilinx, Inc., Altera Corporation. Active years: 2010-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Zhiyuan Wu. Retrieved from https://idiyas.com/inventor/zhiyuan-wu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 73.1

 

Average Co-Inventor Count = 4.8

ph-index = 5

Forward Citations = 97(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2010 - 2012)
  • San Jose, CA (US) (2012 - 2024)

Company Filing History:


Years Active: 2010-2026

Loading Chart...
Loading Chart...
Areas of Expertise:
Selective Passivation
Interconnect Structures
Ruthenium Liner
Copper Electromigration
Cobalt Doping
Microwave Anneal
Seed Layers
Tungsten Via Fill
Hierarchical Layout
Circuit Optimization
Metal Cap Deposition
Diffusion Regions
26 patents (USPTO):Explore Patents

Title: Zhiyuan Wu: A Pioneer in Interconnect Structures

Introduction

Zhiyuan Wu, a distinguished inventor based in San Jose, CA, has made significant contributions to the field of semiconductor technology, particularly in the area of interconnect structures. With an impressive portfolio of 21 patents, Wu has been at the forefront of innovations aimed at enhancing the performance and reliability of electronic devices.

Latest Patents

Among Wu's latest patents are groundbreaking methodologies that improve interconnect structures. One notable patent, titled "Method of forming a metal liner for interconnect structures," includes a process that comprises forming a dielectric layer on a substrate. This innovative method introduces a self-assembled monolayer (SAM) on the substrate's bottom surface, followed by selectively depositing a metal liner atop a barrier layer. This technique not only enhances structural integrity but also optimizes electrical performance.

Another prominent patent, "Doped selective metal caps to improve copper electromigration with ruthenium liner," presents an advanced approach for forming interconnect structures. This patent describes multiple stages including the formation of a barrier layer, a liner layer, and a seed layer, followed by a metal fill process utilizing electroplating. The selective deposition of a cobalt-aluminum alloy cap layer further improves device reliability against copper electromigration.

Career Highlights

Wu has built a remarkable career, contributing his expertise at leading technology companies including Applied Materials, Inc. and Xilinx, Inc. His work has not only been pivotal in advancing semiconductor technology but also in establishing best practices in the industry.

Collaborations

Throughout his career, Wu has collaborated with esteemed professionals in the field, including notable colleagues such as Mehul B Naik and Nikolaos Bekiaris. These collaborations have played a vital role in fostering innovation and pushing the boundaries of semiconductor research.

Conclusion

Zhiyuan Wu’s contributions to semiconductor technology and interconnect structures are noteworthy, reflecting his status as a leading inventor in the field. With a robust patent portfolio and valuable industry collaborations, Wu continues to pave the way for advancements that significantly impact electronic device performance and reliability.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…