The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Apr. 26, 2017
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

He Ren, San Jose, CA (US);

Feiyue Ma, San Jose, CA (US);

Yu Lei, Belmont, CA (US);

Kai Wu, Palo Alto, CA (US);

Mehul B. Naik, San Jose, CA (US);

Zhiyuan Wu, San Jose, CA (US);

Vikash Banthia, Los Altos, CA (US);

Hua Al, Tracy, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/28562 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01);
Abstract

Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.


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