Applied Materials, Inc.

Xilinx, Inc.

Altera Corporation

Zhiyuan Wu

Mehul B Naik

Feng Chen

Tae Hong Ha

Nikolaos Bekiaris

Wenjing Xu

Xianmin Tang

Michael J Hart

He Ren

Lu Chen

Yu Lei

Kai Wu

Vikash Banthia

Jae-Gyung Ahn

John W Cooksey

Ping-Chin Yeh

Yun Wu

Feiyue Ma

Jin Hee Park

Gang Shen

Mark Hyun Lee

Bei Zhu

Srinivas D Nemani

Peter Rabkin

Michael Wayne Stowell, Jr

Ning Cheng

Bencherki Mebarki

Jie Zhou

Myongseob Kim

Kevin Kashefi

Ben-Li Sheu

Christopher J Pass

Qi Lin

Sharmin Sadoughi

Jane W Sowards

Yufei Hu

Meng Chu Tseng

Bang-Thu Nguyen

Prabhuram Gopalan

Hua Ai

Carmen Leal Cervantes

Yizhak Sabba

Min-Hsing Chen

Min-Fang Ho

Hong-Tze Pan

Hua Al

Ge Qu

Yong Jin Kim

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Method of forming a metal liner for interconnect structures

Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.

Doped selective metal caps to improve copper electromigration with ruthenium liner

Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

Ruthenium liner and cap for back-end-of-line

Ruthenium liner and cap for back-end-of-line applications

Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

Binary metal liner layers

Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

Methods and apparatus for forming an interconnect structure, the method including selectively depositing two or more capping layers atop a top surface of a via within a low-k dielectric layer, wherein the two or more capping layers include a first layer of ruthenium and a second layer of cobalt.

Methods for forming cobalt and ruthenium capping layers for interconnect structures

In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

Enhanced cobalt agglomeration resistance and gap-fill performance by ruthenium doping

Methods for forming a copper seed layer having improved anti-migration properties are described herein. In one embodiment, a method includes forming a first copper layer in a feature, forming a ruthenium layer over the first copper layer in the feature, and forming a second copper layer on the ruthenium layer in the feature. The ruthenium layer substantially locks the copper layer there below in place in the feature, preventing substantial physical migration thereof.

Seed layers for copper interconnects

Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

Process integration approach of selective tungsten via fill

An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

Microwave anneal to improve CVD metal gap-fill and throughput

Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.

A transistor device is provided. The transistor device includes a group of fins formed in a substrate, where the group of fins comprises at least one enabled fin and at least one disabled fin. Each of the fins has first and second fin portions. The first fin portion encompasses a drain region and the second fin portion of the fins encompasses a source region. These two regions are separated by a channel region. A gate structure is formed over the fins and channel region and in between the first fin portion and the second fin portion of the fins. The transistor device further includes a conductive structure. The conductive structure shorts the first fin portion of the at least one disabled fin to the second fin portion of the at least one disabled fin.

Methods and apparatuses for optimizing power and functionality in transistors

Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer.

Cobalt resistance recovery by hydrogen anneal

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San Jose, CA, United States of America

Zhiyuan Wu