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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Yung-Fa Chou

This inventor holds 21 USPTO granted patents and 1 published patent application, primarily in Semiconductor Technology. Top assignees: Industrial Technology Research Institute, Taiwan Semiconductor Manufacturing Comp. Ltd., National Tsing Hua University. Active years: 1999-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yung-Fa Chou. Retrieved from https://idiyas.com/inventor/yung-fa-chou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 21 

% Patents Active = 100.0

Average Co-Inventor Count = 1.7

ph-index = 7

Forward Citations = 104(Granted Patents)


Location History:

  • Hsinchu, TW (1999)
  • Kaohsiung, TW (2000 - 2016)

Company Filing History:

goldMedal13 out of 9,308 
 
Industrial Technology Research Institute
 patents
silverMedal7 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
bronzeMedal1 out of 1,308 
 
National Tsing Hua University
 patents

Years Active: 1999-2016

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Areas of Expertise:
Interposer
Memory Device
Semiconductor Device
Through-Silicon-Via
Three-Dimensional Integrated Circuit
Chip Repair
Die Stacking
DRAM Device
SRAM Cell
High-Voltage Switch
Low-Power Circuit
Clamping Circuit
21 patents (USPTO):Explore Patents
1. 9347981 - Test method for interposer (2016-05-24),
2. 9064549 - Memory device (2015-06-23),
3. 9048342 - Semiconductor device stacked structure (2015-06-02),
4. 8937486 - Method for testing through-silicon-via (2015-01-20),
5. 8912015 - Operating method of hardwired switch (2014-12-16),
6. 8854853 - Technology of memory repair after stacking of three-dimensional integrated circuit (2014-10-07),
7. 8710676 - Stacked structure and stacked method for three-dimensional chip (2014-04-29),
8. 8683276 - Apparatus and method for repairing an integrated circuit (2014-03-25),
9. 8384201 - Wafer and method for improving yield rate of wafer (2013-02-26),
10. 8344520 - Stacked structure of chips (2013-01-01),
11. 8217521 - Hardwired switch of die stack and operating method of hardwired switch (2012-07-10),
12. 8193006 - Method of chip repair by stacking a plurality of bad dies (2012-06-05),
13. 8026585 - Die stacking structure and fabricating method thereof (2011-09-27),
14. 7924083 - Isolation circuit (2011-04-12),
15. 6591384 - Comparable circuits for parallel testing DRAM device (2003-07-08),

Title: Yung-Fa Chou: Innovator and Patent Holder from Kaohsiung

Introduction

Yung-Fa Chou is a prominent inventor based in Kaohsiung, Taiwan, known for his remarkable contributions to the field of technology and innovation. With a total of 21 patents to his name, he has developed groundbreaking solutions that have significantly impacted the industry.

Latest Patents

Among his latest inventions, Yung-Fa Chou has developed a test method for an interposer which includes a series of conductive lines and connecting contacts. This innovative test method employs a passive transponder device to conduct open-circuit or short-circuit tests, ensuring the integrity of the interposer. Additionally, he has patented a sophisticated memory device featuring various memory block sizes and decoding circuits, allowing for enhanced control and efficiency in memory operations.

Career Highlights

Yung-Fa Chou has built a distinguished career working with leading technology companies. Notably, he has been associated with the Industrial Technology Research Institute and the Taiwan Semiconductor Manufacturing Company Limited, where he has honed his skills and expertise in semiconductor technology and device innovation.

Collaborations

Throughout his career, Yung-Fa has collaborated with talented professionals like Ding-Ming Kwai and Ting-Sheng Chen. Their teamwork has fostered an environment of creativity and innovation, leading to impactful advancements in their field.

Conclusion

Yung-Fa Chou's commitment to innovation and his extensive patent portfolio underline his significant role in technological advancements. His ongoing contributions continue to inspire future inventors and shape the landscape of modern technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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