The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

May. 01, 2014
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Yung-Fa Chou, Kaohsiung, TW;

Ding-Ming Kwai, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 8/10 (2006.01); G11C 8/14 (2006.01); G11C 5/02 (2006.01); G11C 7/18 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 8/10 (2013.01); G11C 8/14 (2013.01); G11C 5/025 (2013.01); G11C 7/18 (2013.01); G11C 5/14 (2013.01);
Abstract

A memory device including at least one bit-line decoding circuit, at least one word-line decoding circuit, a plurality of memory blocks, and a plurality of switches is provided. The sizes of the plurality of memory blocks include at least one first size and a second size, and the first size is greater than the second size. The plurality of memory blocks with the first size are grouped as at least one first group, and the plurality of memory blocks with the second size are grouped as at least one second group. Compared to the first group, the second group is closer to the bit-line decoding circuit and/or the word-line decoding circuit. The switches are controlled by at least one control signal, so as to enable or disable the first group and/or the second group.


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