The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Apr. 19, 2012
Applicants:

Ding-ming Kwai, Hsinchu County, TW;

Yung-fa Chou, Kaohsiung, TW;

Chiao-ling Lung, Hsinchu County, TW;

Jui-hung Chien, New Taipei, TW;

Inventors:

Ding-Ming Kwai, Hsinchu County, TW;

Yung-Fa Chou, Kaohsiung, TW;

Chiao-Ling Lung, Hsinchu County, TW;

Jui-Hung Chien, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 2224/1301 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1316 (2013.01); H01L 2224/13184 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/94 (2013.01); H01L 2924/3511 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/10253 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01);
Abstract

A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.


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