The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2003
Filed:
Apr. 25, 2000
Yung-Fa Chou, Kaohsiung, TW;
Abstract
A comparable circuit employed for parallel testing DRAM devices is disclosed, wherein the disclosed comparable circuit basically encompasses a three-stage circuit composed of two XNOR gates, a XOR gate, and a tri-state output buffer. The first stage consisting of the XOR gate and a first XNOR gate parallel receive the stored test pattern from the detected memory cell to respectively generate a pair of first comparison results. A second exclusive XNOR gate included in the second stage receives the first comparison results, and connects with the third stage through an output terminal of the second XNOR gate. The third stage composed of the output buffer couples with the output terminal of the second XNOR gate to generate a second comparison result further routed to I/O bus. Chess-like test patterns can be employed in the disclosed comparable circuit due to two mutually exclusive logic gates are generated in the first stage. On the other hand, logic 1 freezes on I/O bus if two input terminals of the second XNOR gate are shorted, which indicates the comparable circuit is defective.