Yen-Hsiu Chen

This inventor holds 14 USPTO granted patents and 7 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2007-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yen-Hsiu Chen. Retrieved from https://idiyas.com/inventor/yen-hsiu-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14 (Patent Applications = 7)

% Patents Active = 100.0

Average Co-Inventor Count = 5.7

ph-index = 1

Forward Citations = 1(Granted Patents)

Company Filing History:

14 out of 42,926

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

Years Active: 2007-2026

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14 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12604552 - Contact etch stop layer for a pixel sensor (2026-04-14),

2. 12369336 - Method and system for forming metal-insulator-metal capacitors (2025-07-22),

3. 12363928 - Surface damage control in diodes (2025-07-15),

4. 12297104 - Semiconductor structure and formation thereof (2025-05-13),

5. 12094756 - Semiconductor arrangement comprising isolation structure comprising at least two electrical insulator layers (2024-09-17),

6. 12046615 - Semiconductor device including deep trench isolation structure comprising dielectric structure and copper structure and method of making the same (2024-07-23),

7. 12040221 - Fabrication method of metal-free SOI wafer (2024-07-16),

8. 11973148 - Surface damage control in diodes (2024-04-30),

9. 11562923 - Semiconductor arrangement including a first electrical insulator layer and a second electrical insulator layer and method of making (2023-01-24),

10. 11502160 - Method and system for forming metal-insulator-metal capacitors (2022-11-15),

11. 11232974 - Fabrication method of metal-free SOI wafer (2022-01-25),

12. 10868156 - Method of forming epitaxial silicon layer and semiconductor device thereof (2020-12-15),

13. 10516040 - Method of forming epitaxial silicon layer and semiconductor device thereof (2019-12-24),

14. 7176081 - Low temperature method for metal deposition (2007-02-13),

Title: Yen-Hsiu Chen: Innovator in Semiconductor Technology

Introduction

Yen-Hsiu Chen is a prominent inventor based in Tainan, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 13 patents. His work focuses on enhancing the performance and reliability of semiconductor devices.

Latest Patents

Among his latest patents is a method and system for forming metal-insulator-metal capacitors. This innovative semiconductor processing system is designed to create a capacitor dielectric layer in a metal-insulator-metal capacitor. It includes a precursor tank that generates a precursor gas from a metal organic solid precursor, a processing chamber for plasma enhanced chemical vapor deposition, and at least one buffer tank connecting the precursor tank and the processing chamber. Another notable patent addresses surface damage control in diodes. This patent describes a semiconductor device and a method of forming it, which includes a substrate with multiple well regions and a metal silicide layer to enhance device performance.

Career Highlights

Yen-Hsiu Chen is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His expertise and innovative approaches have positioned him as a key player in advancing semiconductor technologies.

Collaborations

Yen-Hsiu Chen collaborates with talented individuals in his field, including Yu-Lung Yeh and Yung-Hsiang Chen, who contribute to the development of cutting-edge semiconductor solutions.

Conclusion

Yen-Hsiu Chen's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the industry. His work continues to shape the future of semiconductor devices and processing systems.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

7 patents pending: