The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2024
Filed:
Jan. 19, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Yu-Hung Cheng, Tainan, TW;
Pu-Fang Chen, Hsinchu, TW;
Cheng-Ta Wu, Shueishang Township, TW;
Po-Jung Chiang, Zhongli, TW;
Ru-Liang Lee, Hsinchu, TW;
Victor Y. Lu, Foster City, CA (US);
Yen-Hsiu Chen, Tainan, TW;
Yeur-Luen Tu, Taichung, TW;
Yu-Lung Yeh, Kaohsiung, TW;
Shi-Chieh Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.