The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Apr. 24, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yu-Hung Cheng, Tainan, TW;

Po-Jung Chiang, Taoyuan, TW;

Yen-Hsiu Chen, Tainan, TW;

Yeur-Luen Tu, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/3065 (2006.01); H01L 21/285 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/732 (2006.01);
U.S. Cl.
CPC ...
H01L 29/739 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02609 (2013.01); H01L 21/02636 (2013.01); H01L 21/02639 (2013.01); H01L 21/28518 (2013.01); H01L 21/3065 (2013.01); H01L 21/76895 (2013.01); H01L 29/0649 (2013.01); H01L 29/0813 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/66272 (2013.01); H01L 29/66325 (2013.01); H01L 29/732 (2013.01); H01L 29/7325 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, where a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer with a first growth rate around a sidewall adjacent to the gate structures that is greater than a second growth rate at a central portion; and, in the chamber, partially removing the epitaxial silicon-rich layer with an etchant with a first etching rate around the sidewall adjacent to the gate structures that is greater than a second etching rate at the central portion.


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